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<a href="#pub-attribs">Data Fields</a>  </div>
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<div class="title">NVIC_Type Struct Reference<div class="ingroups"><a class="el" href="group___c_m_s_i_s__core__register.html">Defines and Type Definitions</a> &raquo; <a class="el" href="group___c_m_s_i_s___n_v_i_c.html">Nested Vectored Interrupt Controller (NVIC)</a></div></div>  </div>
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<p>Structure type to access the Nested Vectored Interrupt Controller (NVIC).  
 <a href="struct_n_v_i_c___type.html#details">More...</a></p>

<p><code>#include &lt;<a class="el" href="core__cm0plus_8h_source.html">core_cm0plus.h</a>&gt;</code></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:ab608972d2d0184ba03dc9f4f3fff4f06"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_n_v_i_c___type.html#ab608972d2d0184ba03dc9f4f3fff4f06">ISER</a> [1U]</td></tr>
<tr class="separator:ab608972d2d0184ba03dc9f4f3fff4f06"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a55db8d84d137107ba68063081d909d54"><td class="memItemLeft" align="right" valign="top"><a id="a55db8d84d137107ba68063081d909d54"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><b>RESERVED0</b> [31U]</td></tr>
<tr class="separator:a55db8d84d137107ba68063081d909d54"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6322dd58262ec1a7ea15765d9a8b5e70"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_n_v_i_c___type.html#a6322dd58262ec1a7ea15765d9a8b5e70">ICER</a> [1U]</td></tr>
<tr class="separator:a6322dd58262ec1a7ea15765d9a8b5e70"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a258bda0760e41bcdae343bca08962a36"><td class="memItemLeft" align="right" valign="top"><a id="a258bda0760e41bcdae343bca08962a36"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><b>RSERVED1</b> [31U]</td></tr>
<tr class="separator:a258bda0760e41bcdae343bca08962a36"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a39391701e1ec375637074dd76a35276f"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_n_v_i_c___type.html#a39391701e1ec375637074dd76a35276f">ISPR</a> [1U]</td></tr>
<tr class="separator:a39391701e1ec375637074dd76a35276f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae455b35f289b0b28cecca4b0dc401e12"><td class="memItemLeft" align="right" valign="top"><a id="ae455b35f289b0b28cecca4b0dc401e12"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><b>RESERVED2</b> [31U]</td></tr>
<tr class="separator:ae455b35f289b0b28cecca4b0dc401e12"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a53f4282d43d93f2ddb19764f336ad27d"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_n_v_i_c___type.html#a53f4282d43d93f2ddb19764f336ad27d">ICPR</a> [1U]</td></tr>
<tr class="separator:a53f4282d43d93f2ddb19764f336ad27d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a58893c7e3e932e46ee93876af0193e81"><td class="memItemLeft" align="right" valign="top"><a id="a58893c7e3e932e46ee93876af0193e81"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><b>RESERVED3</b> [31U]</td></tr>
<tr class="separator:a58893c7e3e932e46ee93876af0193e81"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a912eeccb87076693e39c4d8478f0ca1e"><td class="memItemLeft" align="right" valign="top"><a id="a912eeccb87076693e39c4d8478f0ca1e"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><b>RESERVED4</b> [64U]</td></tr>
<tr class="separator:a912eeccb87076693e39c4d8478f0ca1e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a54051f32091607a64e1e044413da3b8b"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_n_v_i_c___type.html#a54051f32091607a64e1e044413da3b8b">IP</a> [8U]</td></tr>
<tr class="separator:a54051f32091607a64e1e044413da3b8b"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p>Structure type to access the Nested Vectored Interrupt Controller (NVIC). </p>
</div><h2 class="groupheader">Field Documentation</h2>
<a id="a6322dd58262ec1a7ea15765d9a8b5e70"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a6322dd58262ec1a7ea15765d9a8b5e70">&#9670;&nbsp;</a></span>ICER</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">__IOM uint32_t ICER[1U]</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Offset: 0x080 (R/W) Interrupt Clear Enable Register </p>

</div>
</div>
<a id="a53f4282d43d93f2ddb19764f336ad27d"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a53f4282d43d93f2ddb19764f336ad27d">&#9670;&nbsp;</a></span>ICPR</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">__IOM uint32_t ICPR[1U]</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Offset: 0x180 (R/W) Interrupt Clear Pending Register </p>

</div>
</div>
<a id="a54051f32091607a64e1e044413da3b8b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a54051f32091607a64e1e044413da3b8b">&#9670;&nbsp;</a></span>IP</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">__IOM uint32_t IP[8U]</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Offset: 0x300 (R/W) Interrupt Priority Register </p>

</div>
</div>
<a id="ab608972d2d0184ba03dc9f4f3fff4f06"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ab608972d2d0184ba03dc9f4f3fff4f06">&#9670;&nbsp;</a></span>ISER</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">__IOM uint32_t ISER[1U]</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Offset: 0x000 (R/W) Interrupt Set Enable Register </p>

</div>
</div>
<a id="a39391701e1ec375637074dd76a35276f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a39391701e1ec375637074dd76a35276f">&#9670;&nbsp;</a></span>ISPR</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">__IOM uint32_t ISPR[1U]</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Offset: 0x100 (R/W) Interrupt Set Pending Register </p>

</div>
</div>
<hr/>The documentation for this struct was generated from the following file:<ul>
<li><a class="el" href="core__cm0plus_8h_source.html">core_cm0plus.h</a></li>
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